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| G -LINK GLT7256L08 Ultra High Performance 3.3V 32K x 8 Bit CMOS STATIC RAM Mar 2000(REV. 2.0) Features : 32K x 8-bit organization. Very high speed - 8,10,12,15 ns. Low standby power. Description : GLT7256L08 are high performance 256K bit static random access memories organized as 32K by 8 bits and operate at a single 3.3 volt supply. Fabricated with G-Link Technology's very advanced CMOS subMaximum 2mA for GLT7256L08. micron technology, GLT7256L08 offer a combination Fully static operation of features: very high speed and very low stand-by 3.3V5% power supply. current. In addition, this device also supports easy TTL compatible I/O. memory expansion with an active LOW chip enable Three state output. ( CE ) as well as an active LOW output enable ( OE ) Chip enable for simple memory expansion. and three state outputs. Available in 28 PIN 300 mil SOJ and TSOP packages. Pin Configurations : Function Block Diagram : GLT7256L08 G-Link Technology Corporation 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation,Taiwan 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. -1- G -LINK GLT7256L08 Ultra High Performance 3.3V 32K x 8 Bit CMOS STATIC RAM Mar 2000(REV. 2.0) Pin Descriptions: Name A0 - A14 CE OE WE I/OO - I/O7 VCC GND Function Address Inputs Chip Enable Input Output Enable Input Write Enable Input Data Input and Data Output +3.3V Power Supply Ground Truth Table: Mode Not Selected (Power Down) Output Disabled Read Write Absolute Maximum Ratings: WE X H H L CE H L L L OE X H L X I/O Operation High Z High Z D OUT DIN VCC Current ICCSB ,ICCSB1 ICC ICC ICC Operation Range: Range Commercial Temperature 0 C to + 70 C o o VCC 3.3V5% Ambient Temperature Under Bias...................................-10C to +80C Storage Temperature(plastic)....-55C to +125C (1) Voltage Relative to GND.............-0.5V to + 4.6V Capacitance T A=25C,f=1.0MHZ : Data Output Current..................................50mA Parameter Conditions Max. Unit Power Dissipation......................................1.0W Sym. 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATING may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CIN CI/O Input Capacitance Input/Output Capacitance VIN=0V VI/O=0V 8 10 pF pF G-Link Technology Corporation 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation,Taiwan 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. -2- G -LINK GLT7256L08 Ultra High Performance 3.3V 32K x 8 Bit CMOS STATIC RAM Mar 2000(REV. 2.0) DC Characteristics Sym. VIL VIH ILI ILO VOL VOH ICC ICCSB Parameter Test Conditions Min. Typ(1) -0.3 2.0 -5 -5 2.4 - Max. +0.8 VCC+0.3 5 5 0.4 -8 -10 -12 -15 110 100 90 90 15 Unit V V A A V V mA mA mA Guaranteed Input Low Voltage (2) Guaranteed Input High Voltage (2) Input Leakage Current VCC=Max., VIN=0V to VCC Output Leakage Current VCC=Max., CE VIH Output Low Voltage VCC=Min.,IOL =8mA Output High Voltage VCC=Min., IOH =-4mA Operating Power Supply VCC=Max., CE VIL, Current II/O=0mA., F=Fmax(3) Standby Power Supply Current VCC=Max., CE VIH, II/O=0mA., F=Fmax(3) VCC=Max., CE VCC.-0.2V, VINVCC. -0.2V or ICCSB1 Power Down Power Supply Current - 2 1. Typical characteristics are at VCC=3.3V, TA=25C. 2. These are absolute values with repeat to device ground and all overshoots due to system or tester noise are included. 3. FMAX=1/tRC. Data Retention (L version only) Sym. VDR Parameter VCC for Data retention Test Conditions CE VCC -0.2V, VINVCC -0.2V or VIN0.2V VDR=2.0V Retention Waveform Min. 2.0 Typ(1) - Max. 3.6 30 - Unit V A ns ns ICCDR(1) Data Retention Current tCDR Chip Deselect to Data Retention Time tR Operating Recovery Time 0 tRC(2) - 1. CE VDR -0.2V, VINVDR -0.2V or VIN0.2V. 2. tRC =Read Cycle Time. G-Link Technology Corporation 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation,Taiwan 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. -3- G -LINK GLT7256L08 Ultra High Performance 3.3V 32K x 8 Bit CMOS STATIC RAM Mar 2000(REV. 2.0) Low VCC Data Retention Waveform (CE Controlled) AC Test Conditions Input Pulse Levels Input Rise and Fall Times Timing Reference Level 0V to 3.0V 3 ns 1.5V AC Test Loads and Waveforms AC Electrical Characteristics (over the commercial operating range) Read Cycle Parameter Name -8 Parameter Read Cycle Time Address Access Time Chip Select Access Time, Output Enable to Output Valid Chip Select to Output Low Z, CE Output Enable to Output in Low Z Chip Deselect to Output in High Z, CE Output Disable to Output in High Z Output Hold from Address Change 3 0 4 4 3 Min 8 Max 8 8 5 3 0 0 0 3 5 5 Min 10 -10 Max 10 10 6 3 0 0 0 3 6 6 Min 12 -12 Max 12 12 7 3 0 0 0 3 6 6 Min 15 -15 Max 15 15 8 Unit ns ns ns ns ns ns ns ns ns tRC tAA tACS tOE tCLZ tOLZ tCHZ tOHZ tOH G-Link Technology Corporation 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation,Taiwan 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. -4- G -LINK GLT7256L08 Ultra High Performance 3.3V 32K x 8 Bit CMOS STATIC RAM Mar 2000(REV. 2.0) Switching Waveform (Read Cycle) READ CYCLE1 (1,2,4) READ CYCLE 2 (1,3,4) READ CYCL E 3 (1) Notes: 1. WE is High for READ Cycle. 2. Device is continuously selected CE VIL. 3. Address valid prior to or coincident with CE transition low and/or transition high. 4. OE VIL. 5. Transition is measured 200mV from steady state with CL=5pF. G-Link Technology Corporation 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation,Taiwan 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. -5- G -LINK GLT7256L08 Ultra High Performance 3.3V 32K x 8 Bit CMOS STATIC RAM Mar 2000(REV. 2.0) AC Electrical Characteristics (over the commercial operating range) Write Cycle Parameter Name -8 Parameter Write Cycle Time Chip Select to End of Write Address Set up Time Address Valid to End of Write Write Pulse Width Write Recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time End of Write to Output Active Min 8 6 0 6 6 0 0 5 0 0 4 Max Min 10 8 0 8 8 0 0 6 0 0 5 -10 Max Min 12 10 0 10 10 0 0 8 0 0 6 -12 Max Min 15 12 0 12 12 0 0 10 0 0 -15 Max Unit ns ns ns ns ns ns ns ns ns tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW 6 Switching Waveforms(Write Cycle) WRITE CYCLE 1 (1) G-Link Technology Corporation 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation,Taiwan 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. -6- G -LINK GLT7256L08 Ultra High Performance 3.3V 32K x 8 Bit CMOS STATIC RAM Mar 2000(REV. 2.0) Switching Waveform (Write Cycle) WRITE CYCLE 2(1,6) Note: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap CE low and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CE or WE going high at the end of write cycle. 4. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE transition, outputs remain in a high impedance state. 6. OE is continuously low ( OE =VIL). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE is low during this period, I/O pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured 200mV from steady state with CL=5pF. 11. tCW is measured from CE going low to the end of write. G-Link Technology Corporation 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation,Taiwan 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. -7- G -LINK GLT7256L08 Ultra High Performance 3.3V 32K x 8 Bit CMOS STATIC RAM Mar 2000(REV. 2.0) Ordering Informstion Part Number GLT7256L08-8J3 GLT7256L08-10J3 GLT7256L08-12J3 GLT7256L08-15J3 GLT7256L08-8TS GLT7256L08-10TS GLT7256L08-12TS GLT7256L08-15TS Cycle Time 8ns 10ns 12ns 15ns 8ns 10ns 12ns 15ns Power Low Power Low Power Low Power Low Power Low Power Low Power Low Power Low Power Package SOJ 300mil 28L SOJ 300mil 28L SOJ 300mil 28L SOJ 300mil 28L TSOP TSOP TSOP TSOP Parts Numbers (Top Mark) Definition : GLT 7 256 L 4 : DRAM 6 : Standard SRAM 7 : Cache SRAM 8 : Synchronous Burst SRAM -SRAM 064 : 8K 256 : 256K 512 : 512K 100 : 1M -DRAM 10 : 1M(C/EDO)* 11 : 1M(C/FPM)* 12 : 1M(H/EDO)* 13 : 1M(H/FPM)* 20 : 2M(EDO) 21 : 2M(FPM) 40 : 4M(EDO) 41 : 4M(FPM) 80 : 8M(EDO) 81 : 8M(FPM) *See note 08 - 10 J3 CONFIG. 04 : x04 08 : x08 16 : x16 32 : x32 SPEED -SRAM 10 : 10ns 12 : 12ns 15 : 15ns 20 : 20ns 70 : 70ns -DRAM 35 : 35ns 40 : 40ns 45 : 45ns 50 : 50ns 60 : 60ns PACKAGE T : PDIP(300mil) TS : TSOP(Type I) TC : TSOP(Type ll) PL : PLCC FA : 300mil SOP FB : 330mil SOP FC : 445mil SOP J3 : 300mil SOJ J4 : 400mil SOJ P : PDIP(600mil) Q : PQFP TQ : TQFP VOLTAGE Blank : 5V L : 3.3V M : Mix Voltage Note : CUCDROM , HUHDD. Example : 1.GLT710008-15T 1Mbit(128Kx8)15ns 5V SRAM PDIP(300mil)Package type. 2.GLT44016-40J4 4Mbit(256Kx16)40ns 5V DRAM SOJ(400mil)Package type. G-Link Technology Corporation 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation,Taiwan 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. -8- G -LINK GLT7256L08 Ultra High Performance 3.3V 32K x 8 Bit CMOS STATIC RAM Mar 2000(REV. 2.0) Package Information 300mil 28 pin Small Outline J-form Package (SOJ) G-Link Technology Corporation 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation,Taiwan 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. -9- G -LINK GLT7256L08 Ultra High Performance 3.3V 32K x 8 Bit CMOS STATIC RAM Mar 2000(REV. 2.0) TSOP 28 pin Plastic Dual Inline Package G-Link Technology Corporation 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation,Taiwan 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. - 10 - |
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